Multiple Choice Questions & Answers on Real Time & embedded System OS

Multiple Choice Questions & Answers on Real Time & embedded System OS

RTOS MCQ

1. Time duration required for scheduling dispatcher to stop one process and start another is known as ____________
a) process latency
b) dispatch latency
c) execution latency
d) interrupt latency
Answer: dispatch latency

2. In rate monotonic scheduling ____________
a) shorter duration job has higher priority
b) longer duration job has higher priority
c) priority does not depend on the duration of the job
d) none of the mentioned
Answer: shorter duration job has higher priority

3. The problem of priority inversion can be solved by ____________
a) priority inheritance protocol
b) priority inversion protocol
c) both priority inheritance and inversion protocol
d) none of the mentioned
Answer: priority inheritance protocol

4. In real time operating system ____________
a) all processes have the same priority
b) a task must be serviced by its deadline period
c) process scheduling can be done only once
d) kernel is not required
Answer: a task must be serviced by its deadline period

5. VxWorks is centered around ____________
a) wind microkernel
b) linux kernel
c) unix kernel
d) none of the mentioned
Answer: wind microkernel

6. For real time operating systems, interrupt latency should be ____________
a) minimal
b) maximum
c) zero
d) dependent on the scheduling
Answer: minimal

7. Hard real time operating system has ______________ jitter than a soft real time operating system.
a) less
b) more
c) equal
d) none of the mentioned
Answer: less

8. Which one of the following is a real time operating system?
a) RTLinux
b) VxWorks
c) Windows CE
d) All of the mentioned
Answer: All of the mentioned

9. Time required to synchronous switch from the context of one thread to the context of another thread is called?
a) threads fly-back time
b) jitter
c) context switch time
d) none of the mentioned
Answer: context switch time

10. In which scheduling certain amount of CPU time is allocated to each process?
a) earliest deadline first scheduling
b) proportional share scheduling
c) equal share scheduling
d) none of the mentioned
Answer: proportional share scheduling

Implementing RT Operating Systems MCQ

1. The amount of memory in a real time system is generally ____________
a) less compared to PCs
b) high compared to PCs
c) same as in PCs
d) they do not have any memory
Answer: less compared to PCs

2. Interrupt latency refers to the period of time ____________
a) from the occurrence of an event to the arrival of an interrupt
b) from the occurrence of an event to the servicing of an interrupt
c) from arrival of an interrupt to the start of the interrupt service routine
d) none of the mentioned
Answer: from arrival of an interrupt to the start of the interrupt service routine

3. The most effective technique to keep dispatch latency low is to ____________
a) provide non preemptive kernels
b) provide preemptive kernels
c) make it user programmed
d) run less number of processes at a time
Answer: provide preemptive kernels

4. Preemptive, priority based scheduling guarantees ____________
a) hard real time functionality
b) soft real time functionality
c) protection of memory
d) none of the mentioned
Answer: soft real time functionality

5. The amount of time required for the scheduling dispatcher to stop one process and start another is known as ______________
a) event latency
b) interrupt latency
c) dispatch latency
d) context switch
Answer: dispatch latency

6. Real time systems must have ____________
a) preemptive kernels
b) non preemptive kernels
c) preemptive kernels or non preemptive kernels
d) neither preemptive nor non preemptive kernels
Answer: preemptive kernels

7. In a real time system the computer results ____________
a) must be produced within a specific deadline period
b) may be produced at any time
c) may be correct
d) all of the mentioned
Answer: must be produced within a specific deadline period

8. Priority inversion is solved by use of _____________
a) priority inheritance protocol
b) two phase lock protocol
c) time protocol
d) all of the mentioned
Answer: priority inheritance protocol

9. In a safety critical system, incorrect operation ____________
a) does not affect much
b) causes minor problems
c) causes major and serious problems
d) none of the mentioned
Answer: does not affect much.

10. Some of the properties of real time systems include ____________
a) single purpose
b) inexpensively mass produced
c) small size
d) all of the mentioned
Answer: all of the mentioned

11. The technique in which the CPU generates physical addresses directly is known as ____________
a) relocation register method
b) real addressing
c) virtual addressing
d) none of the mentioned
Answer: real addressing

12. Real time systems need to __________ 
a) minimize the interrupt latency.
b) maximize the interrupt latency.
c) not bother about
d) none of the mentioned
Answer: minimize the interrupt latency.

13. Antilock brake systems, flight management systems, pacemakers are examples of ____________
a) safety critical system
b) hard real time system
c) soft real time system
d) safety critical system and hard real time system
Answer: safety critical system and hard real time system

14. Memory management units ____________
a) increase the cost of the system
b) increase the power consumption of the system
c) increase the time required to complete an operation
d) all of the mentioned
Answer: all of the mentioned

15. Interrupt latency refers to the period of time ____________
a) from the occurrence of an event to the arrival of an interrupt
b) from the occurrence of an event to the servicing of an interrupt
c) from arrival of an interrupt to the start of the interrupt service routine
d) none of the mentioned
Answer: from arrival of an interrupt to the start of the interrupt service routine

16. In a ______ real time system, it is guaranteed that critical real time tasks will be completed within their deadlines.
a) soft
b) hard
c) critical
d) none of the mentioned
Answer: hard

17. Real time systems need to __________ the interrupt latency.
a) minimize
b) maximize
c) not bother about
d) none of the mentioned
Answer: minimize

18. What is the disadvantage of real addressing mode?
a) there is a lot of cost involved
b) time consumption overhead
c) absence of memory protection between processes
d) restricted access to memory locations by processes
Answer: absence of memory protection between processes

19. What is Event latency?
a) the amount of time an event takes to occur from when the system started
b) the amount of time from the event occurrence till the system stops
c) the amount of time from event occurrence till the event crashes
d) the amount of time that elapses from when an event occurs to when it is serviced.
Answer: the amount of time that elapses from when an event occurs to when it is serviced

20. What is the priority of a real time task?
a) must degrade over time
b) must not degrade over time
c) may degrade over time
d) none of the mentioned
Answer: must not degrade over time

Real Time CPU Scheduling MCQ

1. Using EDF algorithm practically, it is impossible to achieve 100 percent utilization due to __________
a) the cost of context switching
b) interrupt handling
c) power consumption
d) all of the mentioned
Answer: the cost of context switching

2. Rate monotonic scheduling assumes that the __________
a) processing time of a periodic process is same for each CPU burst
b) processing time of a periodic process is different for each CPU burst
c) periods of all processes is the same
d) none of the mentioned
Answer: processing time of a periodic process is same for each CPU burst

3. To schedule the processes, they are considered _________
a) infinitely long
b) periodic
c) heavy weight
d) light weight
Answer: periodic

4. Earliest deadline first algorithm assigns priorities according to ____________
a) periods
b) deadlines
c) burst times
d) none of the mentioned
Answer: deadlines

5. If there are a total of T = 100 shares to be divided among three processes, A, B and C. A is assigned 50 shares, B is assigned 15 shares and C is assigned 20 shares.
If a new process D requested 30 shares, the admission controller would __________
a) allocate 30 shares to it
b) deny entry to D in the system
c) all of the mentioned
d) none of the mentioned
Answer: deny entry to D in the system

6. The scheduler admits a process using __________
a) two phase locking protocol
b) admission control algorithm
c) busy wait polling
d) none of the mentioned
Answer: busy wait polling

7. If a set of processes cannot be scheduled by rate monotonic scheduling algorithm, then __________
a) they can be scheduled by EDF algorithm
b) they cannot be scheduled by EDF algorithm
c) they cannot be scheduled by any other algorithm
d) none of the mentioned
Answer: they cannot be scheduled by any other algorithm

8. T shares of time are allocated among all processes out of N shares in __________ scheduling algorithm.
a) rate monotonic
b) proportional share
c) earliest deadline first
d) none of the mentioned
Answer: proportional share

9. In rate monotonic scheduling, a process with a shorter period is assigned __________
a) a higher priority
b) a lower priority
c) higher & lower priority
d) none of the mentioned
Answer: a higher priority

10. A process P1 has a period of 50 and a CPU burst of t1 = 25, P2 has a period of 80 and a CPU burst of 35. The total CPU utilization is ____________.
a) 0.90
b) 0.74
c) 0.94
d) 0.80
Answer: 0.94

11. If there are a total of T = 100 shares to be divided among three processes, A, B and C. A is assigned 50 shares, B is assigned 15 shares and C is assigned 20 shares.
A will have ______ percent of the total processor time.
a) 20
b) 15
c) 50
d) none of the mentioned
Answer: 50

12. If there are a total of T = 100 shares to be divided among three processes, A, B and C. A is assigned 50 shares, B is assigned 15 shares and C is assigned 20 shares.
B will have ______ percent of the total processor time.
a) 20
b) 15
c) 50
d) none of the mentioned
Answer: 15

13. If there are a total of T = 100 shares to be divided among three processes, A, B and C. A is assigned 50 shares, B is assigned 15 shares and C is assigned 20 shares.
C will have ______ percent of the total processor time.
a) 20
b) 15
c) 50
d) none of the mentioned
Answer: 20

14. A process P1 has a period of 50 and a CPU burst of t1 = 25, P2 has a period of 80 and a CPU burst of 35. The total CPU utilization is ?
a) 0.90
b) 0.74
c) 0.94
d) 0.80
Answer: 0.94

15. The ____________ scheduling algorithm schedules periodic tasks using a static priority policy with preemption.
a) earliest deadline first
b) rate monotonic
c) first cum first served
d) priority
Answer: rate monotonic

16. If the period of a process is ‘p’, then what is the rate of the task?
a) p2
b) 2*p
c) 1/p
d) p
Answer: 1/p

17. A process P1 has a period of 50 and a CPU burst of t1 = 25, P2 has a period of 80 and a CPU burst of 35., the priorities of P1 and P2 are?
a) remain the same throughout
b) keep varying from time to time
c) may or may not be change
d) none of the mentioned
Answer: keep varying from time to time

18. A process P1 has a period of 50 and a CPU burst of t1 = 25, P2 has a period of 80 and a CPU burst of 35., can the two processes be scheduled using the EDF algorithm without missing their respective deadlines?
a) Yes
b) No
c) Maybe
d) None of the mentioned
Answer: Yes

19. There are two processes P1 and P2, whose periods are 50 and 100 respectively. P1 is assigned higher priority than P2. The processing times are t1 = 20 for P1 and t2 = 35 for P2. Is it possible to schedule these tasks so that each meets its deadline using Rate monotonic scheduling?
a) yes
b) no
c) maybe
d) none of the mentioned
Answer: yes

20. A process P1 has a period of 50 and a CPU burst of t1 = 25, P2 has a period of 80 and a CPU burst of 35. Can the processes be scheduled without missing the deadlines?
a) Yes
b) No
c) Maybe
d) None of the mentioned
Answer: No

Interrupt Routines in RTOS environment MCQ

1. Into how many parts does the interrupt can split the software?
a) 2
b) 3
c) 4
d) 5
Answer: 2

2. What does ISR stand for?
a) interrupt standard routine
b) interrupt service routine
c) interrupt software routine
d) interrupt synchronous routine
Answer: interrupt service routine

3. An interrupt breaks the execution of instructions and diverts its execution to
a) Interrupt service routine
b) Counter word register
c) Execution unit
d) control unit
Answer: Interrupt service routine

4. If any interrupt request given to an input pin cannot be disabled by any means then the input pin is called
a) maskable interrupt
b) nonmaskable interrupt
c) maskable interrupt and nonmaskable interrupt
d) none of the mentioned
Answer: nonmaskable interrupt

5. Whenever a number of devices interrupt a CPU at a time, and if the processor is able to handle them properly, it is said to have
a) interrupt handling ability
b) interrupt processing ability
c) multiple interrupt processing ability
d) multiple interrupt executing ability
Answer: multiple interrupt processing ability

6. The INTR interrupt may be
a) maskable
b) nonmaskable
c) maskable and nonmaskable
d) none of the mentioned
Answer: maskable

7. NMI stands for
a) nonmaskable interrupt
b) nonmultiple interrupt
c) nonmovable interrupt
d) none of the mentioned
Answer: nonmaskable interrupt

8. While CPU is executing a program, an interrupt exists then it
a) follows the next instruction in the program
b) jumps to instruction in other registers
c) breaks the normal sequence of execution of instructions
d) stops executing the program
Answer: breaks the normal sequence of execution of instructions

9. The Programmable interrupt controller is required to
a) handle one interrupt request
b) handle one or more interrupt requests at a time
c) handle one or more interrupt requests with a delay
d) handle no interrupt request
Answer: handle one or more interrupt requests at a time

10. The INTR interrupt may be masked using the flag
a) direction flag
b) overflow flag
c) interrupt flag
d) sign flag
Answer: interrupt flag

11. Which of the following allows the splitting of the software?
a) wait statement
b) ready
c) interrupt
d) acknowledgement
Answer: interrupt

12. Which of the following can improve the quality and the structure of a code?
a) polling
b) subroutine
c) sequential code
d) concurrent code
Answer: subroutine

13. Which part of the software is transparent to the interrupt mechanism?
a) background
b) foreground
c) both background and foreground
d) lateral ground
Answer: background

14. Which code is written as part of the ISR?
a) data receive code
b) sequential code
c) data transfer code
d) concurrent code
Answer: data transfer code

15. Which part of the software performs tasks in response to the interrupts?
a) background
b) foreground
c) lateral ground
d) both foreground and background
Answer: foreground

16. Which factor depends on the number of times of polling the port while executing the task?
a) data
b) data transfer rate
c) data size
d) number of bits
Answer: data transfer rate

17. Which can activate the ISR?
a) interrupt
b) function
c) procedure
d) structure
Answer: interrupt

18. The time taken to respond to an interrupt is known as
a) interrupt delay
b) interrupt time
c) interrupt latency
d) interrupt function
Answer: interrupt latency

19. Which of the following can be used to create time-driven systems?
a) memory
b) input
c) output
d) interrupts
Answer: interrupts

20. While executing the main program, if two or more interrupts occur, then the sequence of appearance of interrupts is called
a) multi-interrupt
b) nested interrupt
c) interrupt within interrupt
d) nested interrupt and interrupt within interrupt
Answer: nested interrupt and interrupt within interrupt

21. Which of the following are asynchronous to the operation?
a) interrupts
b) software
c) DMA
d) memory
Answer: interrupts

22. In which of the following method does the code is written in a straight sequence?
a) method 1
b) timing method
c) sequence method
d) spaghetti method
Answer: spaghetti method

23. Whenever a number of devices interrupt a CPU at a time, and if the processor is able to handle them properly, it is said to have
a) interrupt handling ability
b) interrupt processing ability
c) multiple interrupt processing ability
d) multiple interrupt executing ability
Answer: multiple interrupt processing ability

24. NMI stands for
a) nonmaskable interrupt
b) nonmultiple interrupt
c) nonmovable interrupt
d) none of the mentioned
Answer: nonmaskable interrupt

25. The INTR interrupt may be
a) maskable
b) nonmaskable
c) maskable and nonmaskable
d) none of the mentioned
Answer: maskable

Comments