Phase Locked Loop multiple choice questions

 Phase Locked Loop 

1. At what range the PLL can maintain the lock in the circuit?
a) Lock in range
b) Input range
c) Feedback loop range
d) None of the mentioned
Answer: Lock in range
2. At which state the phase-locked loop tracks any change in input frequency?
a) Free running state
b) Capture state
c) Phase locked state
d) All of the mentioned
Answer: Phase locked state
3. The output voltage of phase detector is
a) Phase voltage
b) Free running voltage
c) Error voltage
d) None of the mentioned
Answer: Error voltage
4. Free running multivibrator is also called as
a) Stable multivibrator
b) Voltage control oscillator
c) Square wave oscillator
d) Pulse stretcher
Answer: Voltage control oscillator
5. What is the function of low pass filter in phase-locked loop?
a) Improves low frequency noise
b) Removes high frequency noise
c) Tracks the voltage changes
d) Changes the input frequency
Answer: Removes high frequency noise
6. What is the need to generate corrective control voltage?
a) To maintain the lock
b) To track the frequency change
c) To shift the VCO frequency
d) All of the mentioned
Answer: All of the mentioned
7. The pull-in time depends on
a) Initial phase and frequency difference between two sign
b) Overall loop gain
c) Loop filter characteristics
d) All of the mentioned
Answer: All of the mentioned
8. The aligning of output phase of voltage controlled oscillator with reference is called:
a) Phase compensation
b) Phase alignment
c) Phase Locking
d) Phase detecting
Answer: Phase Locking
9. If the input of type 1 PLL is a frequency step of Δw at t = 0, the change in phase at t = infinity is:
a) Δw
b) Δw/Kpd
c) Δw/Kpd.Kvco
d) None of the mentioned
Answer: Δw/Kpd.Kvco
10. The Logic gate that works similar to phase detector is:
a) AND gate
b) OR gate
c) XOR gate
d) NOT gate
Answer: XOR gate
11. Number of poles in Type 1 PLL is:
a) 0
b) 1
c) 2
d) None of the mentioned
Answer: 2
12. The PLL device is:
a) Feedback system that compares output frequency and input frequency
b) Feedback system that compares output phase and input phase
c) Linear system that compares output resistance and input resistance
d) Non Linear system that compares output current and input current
Answer: Feedback system that compares output phase and input phase
13. If high pass filter is used instead of Low pass filter in the PLL the response of PLL would be:
a) Output Voltage is not a square wave
b) Output Voltage contains many high frequency waves
c) VCO will be unstable due to variations in control voltage
d) All of the mentioned
Answer: Output Voltage contains many high frequency waves
14. The transfer function of PD is :
a) Constant
b) Varies with frequency
c) Varies with voltage
d) None of the Mentioned
Answer: Constant
15. Instead of Phase detection, if Frequency detector is used the drawback PLL would face is:
a) Finite difference between input and output frequency
b) Equality cannot be established if PLL compared input and output frequency rather than pulses
c) Error between Vin and Vout cannot be removed
d) All of the mentioned
Answer: All of the mentioned
16. Which characteristic of PLL is defined as the range of frequencies over which PLL can acquire lock with the input signal?
a) Free-running state
b) Pull-in time
c) Lock-in range
d) Capture range
Answer: Capture range
17. According to transfer characteristics of PLL, the phase error between VCO output & incoming signal must be maintained between _______ in order to maintain a lock.
a) 0 & π
b) 0 & π/2
c) 0 & 2Ï€
d) π & 2π
Answer: 0 & π
18. Basically, PLL is used to lock _______
a) Its output frequency
b) Phase to the frequency
c) Phase of the input signal
d) All of the above
Answer: All of the above
19. In the locked state of PLL, the phase error between the input & output is _________.
a) Maximum
b) Moderate
c) Minimum
d) All of the above
Answer: Minimum
20. In AM detector using PLL, the phase detector is basically a multiplier which produces ______ components of frequencies at its output.
a) Sum
b) Difference
c) Both a and b
d) None of the above
Answer: Both a and b
21. In PLL, the capture range is always _______ the lock range.
a) Greater than
b)  Equal to
c) Less than
d) None of the above
Answer: Less than
22. For a PLL IC 565 with timing resistor & timing capacitor of about 15 kΩ & 0.02μF respectively, what would be the value of output frequency (f0)?
a) 433.33 Hz
b) 833.33 Hz
c) 1000 Hz
d) 2500 Hz
Answer: 833.33 Hz
23. In VCO IC 566, the value of charging & discharging is dependent on the voltage applied at ______.
a) Triangular wave output
b) Square wave output
c) Modulating input
d) All of the above
Answer: Modulating input
24. In communication circuits, PLL is currently applicable for __________
a) Demodulation applications
b) Tracking a carrier or synchronizing signal
c) Both a and b
d) None of the above
Answer: Both a and b
25. Once the phase is locked, the PLL tracks the variation in the input frequency. This indicates that _____
a) Output frequency changes by same amount as that of input frequency
b) Output frequency does not change as that of input frequency
c) There is no relation between input & output frequencies
d) None of the above
Answer: Output frequency changes by same amount as that of input frequency

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